1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device provided with an internal supply voltage deboosting circuit.
2. Description of the Prior Art
With the advance of the microminiaturization of elements of semiconductor integrated circuits, there arises a problem in that when an ordinary (e.g., 5 V) external supply voltage Vcc is applied to the elements, the gate oxide films are destroyed or hot carriers are generated, thus causing deterioration of the circuit reliability. In order to secure the reliability of the microminiaturized elements such as transistors of the semiconductor memory device in particular, the memory device is required to include an internal supply voltage deboosting circuit for deboosting an external supply voltage within the chip to reduce voltage stress on the device. Further, where the external supply voltage is deboosted, it is possible to reduce the power consumption of the device and thereby to improve the battery backup time intervals of an electronic apparatus such as a portable personal computer.
FIG. 21 shows a prior art internal supply voltage deboosting circuit, by way of example. This prior art deboosting circuit is composed of a reference potential generating circuit 121, a P-channel transistor P103 for driving an internal supply voltage V.sub.int, a current mirror type differential amplifier 122 made up of P-channel transistors P101 and P102 for controlling the switching operation of the P-channel transistor P103 and N-channel transistors N101 to N103, and resistors R101 and R102.
The referential potential generating circuit 121 generates a reference potential V.sub.ref on the basis of an external supply voltage Vcc. On the other hand, a voltage difference between an internal supply voltage V.sub.int (outputted from the P-channel transistor P103) and a ground voltage Vss is divided by the two resistors R101 and R102, and the divided voltage is outputted as a potential V.sub.A.
The reference voltage V.sub.ref and the potential V.sub.A are inputted to the gates of the two N-channel transistors N101 and N102 of the differential amplifier 122, respectively. When the external supply voltage Vcc is relatively low, since the potential V.sub.A is lower than the reference voltage V.sub.ref, an output voltage V.sub.B of the differential amplifier 122 is at a low level, so that the P-channel transistor P103 is turned on. Here, when the dimensions of the P-channel transistor P103 are determined so that the resistance of the transistor P103 is to be sufficiently smaller than those of the resistors R101 and R102, it is possible to obtain an internal supply voltage V.sub.int roughly equal to the external supply voltage Vcc.
In contrast with this, when the external supply voltage Vcc is relatively high, since the potential V.sub.A is higher than the reference voltage V.sub.ref, the output voltage V.sub.B of the differential amplifier 122 is at a high level, so that the P-channel transistor P103 is turned off. Therefore, the level of the internal supply voltage V.sub.int drops because the voltage V.sub.int int is discharged through the resistors R01 and R102. Here, when the potential V.sub.A becomes lower than the reference voltage V.sub.ref, since the P-channel transistor P103 is turned on again, the internal supply voltage V.sub.int is kept at a constant level. As a result, it is possible to keep the internal supply voltage V.sub.int at a constant level at a point where the potential V.sub.A becomes equal to the reference voltage V.sub.ref.
As described above, when the external supply voltage Vcc is relatively low, the reference voltage V.sub.ref is higher than the potential V.sub.A, so that it is possible to obtain the internal supply voltage V.sub.int roughly equal to the external supply voltage Vcc. On the other hand, when the external supply voltage Vcc is relatively high, the internal supply voltage V.sub.int is kept at a constant level at a point where the reference voltage V.sub.ref becomes equal to the potential V.sub.A,
FIG. 22 shows a practical circuit construction of the reference potential generating circuit 21, and FIG. 23 shows the characteristics between the reference potential V.sub.ref, the internal supply voltage V.sub.int and the external supply voltage Vcc, which are obtained by the circuit shown in FIG. 22.
The reference potential generating circuit 21 is composed of two circuits 131 and 132. The circuit 131 serves to determine the characteristics of the reference voltage V.sub.ref when the external supply voltage Vcc ranges between 0 V and V.sub.cur. Here, the voltage V.sub.cur corresponds to the external supply voltage Vcc obtained when the reference voltage V.sub.ref becomes equal to a voltage V.sub.E of the circuit 132 (described later). Further, the circuit 132 serves to determine the characteristics of the reference voltage V.sub.ref obtained when the supply voltage Vcc is higher than the voltage V.sub.cur.
In the circuit 131, two resistors R103 and R104 and a P-channel transistor P104 are connected in series between the external supply voltage Vcc and the ground voltage Vss. A voltage V.sub.C can be generated from a node between the two resistors R103 and R104. Here, since the resistance value of the resistor R103 is determined to be sufficiently higher than that of the resistor R104, the voltage V.sub.C can be set to a constant level almost without being dependent upon the external supply voltage Vcc.
This generated voltage V.sub.C is inputted to a differential amplifier 141 composed of two P-channel transistors P105 and P106 and three N-channel transistors N104 to N106. Further, a P-channel transistor P107 and two resistors R105 and R106 are connected in series between the external supply voltage Vcc and the ground voltage Vss. A voltage V.sub.D can be generated from a node between the two resistors R105 and R106. Further, these two voltages V.sub.D and V.sub.C are both inputted to the differential amplifier 141. In the circuit 131, in the same way as with the case of the circuit as shown in FIG. 21, when the external supply voltage Vcc is relatively high, the reference voltage V.sub.ref outputted from a node between the P-channel transistor P107 and the resistor R105 is kept at a constant level. Here, in the case of the circuit shown in FIG. 21, the resistance of the P-channel transistor P103 is determined to be sufficiently smaller than those of the resistors R101 and R102. In the case of the circuit 131 shown in FIG. 22, however, the resistance of the P-channel transistor P107 is determined to be sufficiently larger than those of the resistors R105 and R106. This is because the voltage V.sub.D must be determined by the resistance division of the P-channel transistor P107 and the resistor R105, and the resistor R106.
The circuit 132 includes two resistors R107 and R108, a differential amplifier 142, and a driving P-channel transistor P108. A potential V.sub.E obtained by dividing the external supply voltage Vcc by the two resistors R107 and R108, and the reference potential V.sub.ref are both inputted to the reference amplifier 142 for comparison of both.
When the external supply voltage Vcc ranges between 0 V and V.sub.cur, the reference voltage V.sub.ref becomes higher than the potential V.sub.E. In this case, an output voltage V.sub.G of the differential amplifier 142 becomes a high level, so that the P-channel transistor P108 is turned off. Accordingly, the reference potential V.sub.ref can be determined by only the circuit 131.
When the external supply voltage Vcc becomes higher than the potential V.sub.cur, the reference voltage V.sub.ref becomes lower than the potential V.sub.E. Therefore, the output voltage V.sub.G of the differential amplifier 142 becomes a low level, so that the P-channel transistor P108 is turned on. Once the P-channel transistor P108 is turned on, the voltage V.sub.D of the circuit 131 rises. Accordingly, an output voltage V.sub.F of the differential amplifier 141 of the circuit 131 becomes the high level, so that the P-channel transistor P107 is turned off. As a result, the reference potential V.sub.ref can be determined by only the circuit 132. When the external supply voltage Vcc further rises, the reference voltage V.sub.ref also rises.
Further, in FIG. 23, the internal supply voltage V.sub.int rises in a range in which the external supply voltage Vcc is higher than the voltage V.sub.cur. This is because in the case of products whose external supply voltage Vcc is 5 V, although the voltage range to be used is between 4.5 V and 5 V, a burn-in test must be performed in a voltage range higher than the above-mentioned range.
As described above, conventionally, the internal supply voltage has been generated by deboosting the external supply voltage with the use of the circuit as shown in FIGS. 21 and 22. Recently, however, since lower power consumption is required more and more in portable electronic apparatus, a lower supply voltage is required more and more for the DRAM in the same manner in the CPU.
Therefore, it has been required that the same circuit be used for both products activated by two external supply voltages Vcc=5 V and 3.3 V. In this case, when the external supply voltage Vcc is 5 V, an internal supply voltage deboosting circuit for deboosting the external supply voltage from 5 V to 4 V is required. When the external supply voltage Vcc is 3.3 V, however, no internal supply voltage deboosting circuit is required. In the conventional semiconductor device, however, since the internal supply voltage deboosting circuit is being activated even when the external supply voltage Vcc is 3.3 V, there exists a problem in that the current consumption cannot be reduced.
Further, in FIG. 21, since the internal supply voltage V.sub.int is generated by the P-channel transistor P103, the dimensions of this transistor have been important. When the external supply voltage Vcc is 3.3 V, it has been necessary to determine the dimensions of the P-channel transistors P103 to be as large as possible. This is because when the dimensions of the transistor are small, the voltage drops, with the result that only an internal supply voltage V.sub.int lower than 3.3 V is obtained.
In contrast with this, when the external supply voltage Vcc is high, even if the dimensions of the transistor are small, the influence upon the operational margin is small. In this case, it is rather preferable to determine the dimensions of the P-channel transistors P103 to be small to reduce the switching noise thereof.
As described above, in the conventional semiconductor device, it has been difficult to cope with both the cases where the external supply voltage Vcc is high and low, because the optimum dimensions of the driving transistor are different from each other.
Further, as another example, there exists the semiconductor device having the internal supply voltage deboosting circuit provided with an output buffer circuit. In this case, since output transistor used for the output buffer circuit becomes low in conductance when the external supply voltage Vcc is low, the current driving faculty is inevitably deteriorated. The deterioration of the driving faculty of the output transistor causes a drop of the access speed. To prevent this phenomenon, the dimensions of the output transistor must be increased. When the external supply voltage Vcc is high, however, another problem is caused in that the switching noise of the transistor increases, so that the margin to the high and low levels of the input signal decreases.
Further, the semiconductor device having the internal supply voltage deboosting circuit is sometimes provided with a sense amplifier circuit. In this case, the sense amplifier is usually composed of a P-channel sense amplifier composed of P-channel transistors and an N-channel sense amplifier composed of N-channel transistors. When data stored in the memory cells are read, the P-channel transistors are activated by charging the common source node by the external supply voltage Vcc until the potential thereat reaches the internal supply voltage V.sub.int.
When the common source node is charged, the reference voltage V.sub.RSAP must be determined to be low to reduce the switching noise when the external supply voltage Vcc is high. However, when the external supply voltage Vcc is low, if the reference voltage V.sub.RSAP the same as when the external supply voltage Vcc is high is used, there exists a problem in that it takes a long charging time, so that it is impossible to restore the bit lines sufficiently within a predetermined time period.